Abstract:
The fluid structure interaction (FSI) analysis is implemented on the molded package during the encapsulation process with different velocity inlet. The stacked chip model is constructed using design modular and simulated using FLUENT computational fluid dynamic (CFD) software. The interaction between the fluid and the structure was observed. The visualization of the 3D stacking-chip package encapsulation process was presented at different velocity. The void formation around the stacking chips was identified for each case. The stress concentration was identified for the copper through-silicon vias were determined. The present FSI analysis approach is expected to be a guideline or reference and provides better understanding of the encapsulation process for package design in the microelectronic industry.3-D packaging is a technology which has high density packaging options and offered high performance. It enables chips to be stack in a single package and widely adopted in portable multi-media products. However, thermosetting material flow through a thin space and wide filling area during package encapsulation process has become vital concern i.e. void formation. In this paper, such issue has been numerical studied due to the effect of vent arrangement, chip stacking and transfer speed of the plunger head during encapsulation process in the microelectronic package. These studies have been done in order to investigate the quality of air entrapped (hereafter namely as void), where it degraded the package’s reliability. It was found that the original package and longest transfer speed delivered to the best encapsulation process, which had lowest volume of air trap or void formation.
