SYSTEMATIC MECHANICAL PERFORMANCE STUDY FOR SILICON CHIP IN ELECTRONIC PACKAGING USING UNIFIED APPROACH

Abstract

Ultra-thin chip technology has the potential as the possible solution on overcoming the bottlenecks in silicon technology for new miniaturized applications. However, it increases the potential mechanical risk with such ultra-thin silicon chip solution and requires a comprehensive understanding to appropriately characterize its mechanical integrity and fracture. Hence, the lack of a full structural study from initial silicon chip break strength (SBS) study, to the interaction impact from assembly processes on a final assembled thin packages' silicon chip stress has been identified as the opportunity on this research work. A four stages unified approach for potential silicon chip cracking risk quantification is proposed. First, a simple and practical experimental three pint bend (3PB) SBS investigation with beam theory was initially carried out to study the key silicon process parameters without a need to undergo a complex and heavy computational analysis. Simultaneously, a useful stress-based modeling approach on those critical factors as identified in design, test process and reliability were carried out to analyze and predict the silicon surface stress parametrically. Then, a practical application integrating both experiment and modeling through a universal defect metric with bending stress, namely is established. The realistic risk analysis on those identified electronic packaging (EP) design options and test interaction could be easily predicted, although the preliminary assessment showed an approximately 40% of survival margin for an ideal conditions initially. However, with further inclusion of the critical safety factors, combining the laser marked SBS and higher chip surface stress build up in reliability test, the margin was reduced to <5%, which revealed the significance of this newly developed unified approach in predicting the realistic mechanical assessment for the EP's silicon chip. Besides, a further study was extended to explore a potential and cost effective SBS enhancement option with surface protection opportunity, which improved the SBS by approximately 33%, and validated to be transparent to existing process flow. Through the few test cases with unified approach, it was also suggested that a better EP stiffness control along with a surface protection like the overmold (OM) EP solution was needed for better ultra-thin chip performance enhancement. The completion of this research produced a good benchmark on the effectiveness of systematic unified approach to quantify the ultra-thin silicon chip cracking risk. This unified assessment with a well-structured four phases of research study drives for a potential optimization in design, material and process selection, as well as enhancement opportunity to improve the EP's silicon chip mechanical performance. This approach enables a quick and direct risk level assessment on various critical factors for potential silicon chip cracking failure avoidance.