PREDICTION EQUATIONS AND CHAOS THEORY PHASE-SPACE MODELING FOR A SEMICONDUCTOR MANUFACTURING PERFORMANCE IMPROVEMENT

Abstract

Semiconductor industry's Automatic Test Equipment's (ATE) unpredictable performance in testing microchip units is partly caused by variability, an inherent manufacturing process characteristic that inspires this research. The research objective is to explore the degree of variability in ATE performance and model the behavior to improve equipment capacity forecasting in the semiconductor manufacturing industry. A relationship-based research was designed using five different ATEs dataset comprising 6 variables: Production Time (PT), Idling Time (IT), Repair Time (RT), Awaiting Technician Time (AWTT), Setup Time (ST) and Engineering Time (ET) parameters as input variables, and Production Yield (PY) as output variable. Initially, a manufacturing simulation algorithm imitating a 12-hour shift process running 10000 microchip units with 3. 80 seconds/unit process time and normalized IT, RT, AWTT, ST, and ET was developed and executed in Arena simulation software to establish ATE performance variability. Secondly, the Chaos Theo1y Phase-Space diagrams were developed to visualize chronologically ordered ATE performance variability in an arbitrary phase-space domain. Thirdly, Linear and Polynomial Regression methods using scatterplot, homoscedasticity, normality, p, F-statistic and R Square curve fitting assessments were used to develop and validate 29 prediction equations which link equipment usage (input) to production yield (output). All these equations were solved to acquire maximum Production Yield. Fourthly, the resulting model is validated using the industry's Machine Utilization (MU) capacity equation, with 10% initial Protective Capacity, buffer capacity for production. The manufacturing simulation analysis demonstrated a manufacturing bottleneck where 84 out of 10826 microchip units spent up to 5 .3 591 minutes in the process against average 0.7474 minutes with 95.23% ATE utilization rate. The Phase-Space diagrams analysis illustrated that PY vs. PT and PY vs. ET diagrams imitate period two attractor of chaos theory or predictable (non-chaotic) patterns. IT, RT, AWTT, and ST demonstrate varying degree of chaotic (unpredictable) equipment performance. Linear and Polynomial Regression analysis shows PY vs. PT behaves Linearly Positive, where PT increases, PY increases. PY vs. AWTT, RT, ST, and ET, act Linearly Negative, where AWTT, RT, ST, and ET increases, PY decreases. PY vs. IT exhibits chaotic behavior. By solving these equations to acquire Maximum PY, more accurate figures like Idling Time Maximum can be substituted into the capacity model. Together with the Protective Capacity removal from MU, 9% - 10% Run Rate increase can be achieved equipment-wide, which improves equipment capacity forecast. The 'Acknowledge­Visualize-Model-Validate' model initially developed for the semiconductor-testing industry can be applied to other industry's process variability.