A Reduced Complexity Algorithm of the Butterfly Trellis Unit for the Viterbi Decoder

Abstract

Together with convolutional encoders, Viterbi decoders are commonly used to provide an excellent probability of error correction in wireless transmission. The encoder constraint length k must be set at higher values to achieve an improved bit error rate. With the growth of the Internet of Things (IoT) in recent years, there is inevitable demand for low-power IoT applications. Unfortunately, an increase in the value of k causes the complexity of the algorithm to increase exponentially. Consequently, the Viterbi decoder's power consumption will increase exponentially, which is a detriment to many wireless communication devices. Many of the Viterbi decoder's reduced complexity decoding approaches discussed in the past concentrated on the particular level of algorithms and architectures. Most of the studies focused on the difficulty of the decoder's Add-Compare Select Unit (ACSU) repetitive processing. This paper analyzes many variations carried out in the ACSU of the Viterbi algorithm. Several separate algorithms were compared and an approach to a combined algorithm was suggested. This paper offered an in-depth description of the reduced computation and its design for the proposed algorithm. Each algorithm and reduced complexity are compared with the conventional VD. The impact of power consumption is evaluated through the bit-error-rate (BER) vs Signal-to-Noise ratio (SNR), such that the proposed algorithm was found to have the best dB gain between 0 dB and 5 dB, indicating a significant power improvement over the other algorithms. © 2022, The Aeronautical and Astronautical Society of the Republic of China. All right reserved