Hardware Implementation Of The Bicubic Interpolation For Vein Enhancement Biometric System

Abstract

In this paper, hardware implementation of bicubic interpolation for vein enhancement biometric system is proposed. This paper present hardware architecture that enable pipelining computation with less hardware resource that elude redundant computation, reduce computation complexity and improve the throughput. The architecture utilized parallel pipeline hardware to achieve fast processing time and high throughput. Using temporary interpolation points (TIPs), the offchip memory is accessed only once and redundant memory access is avoided. The TIPs are shifted using shift registers between blocks so its do not need to be calculated again. For the interpolation process, instead of using multipliers, shifters are used to reduce hardware cost and size. Shift registers are used as intermediate buffer between horizontal and vertical interpolation so that memory buffer or FIFO is not required. Experimental results and analysis show that the proposed hardware implementation architecture is efficient, use less hardware resources and speeds up the processing time.